The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs or MOS transistors). The ICs are usually formed using both P-channel and N-channel FETs and the IC is then referred to as a complementary MOS or CMOS integrated circuit (IC). There is a continuing trend to incorporate more and more circuitry on a single IC chip. To incorporate the increasing amount of circuitry the size of each individual device in the circuit and the size and spacing between device elements (the feature size) must decrease. The individual elements of the circuits, MOS transistors and other passive and active circuit elements, must be interconnected by metal or other conductors to implement the desired circuit function. Some small resistance is associated with each contact between the conductor and the circuit element. As the feature size decreases, the contact resistance increases and becomes a greater and greater percentage of the total circuit resistance. As feature sizes decrease from 150 nanometer (nm) to 90 nm, then to 45 nm and below the contact resistance becomes more and more important. At feature sizes of 32 nm the contact resistance likely will dominate chip performance unless some innovation changes the present trend.
Accordingly, it is desirable to provide low contact resistance CMOS integrated circuits. In addition, it is desirable to provide methods for fabricating low contact resistance CMOS integrated circuits. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.